Phase Lock Loops (PLLs) are generally considered clock multipliers. For example, an input reference clock having a frequency of 10 Mhz can be multiplied by the PLL to yield an output clock signal having a frequency of 200 Mhz. Ideally, this clock multiplication would result in an output clock that is in perfect phase/frequency with the reference clock. A phase frequency detector (PFD) is used to generate the proper frequency.
FIG. 1 illustrates a conventional phase lock loop circuit 10. The circuit 10 has a phase frequency detector (PFD) 12, a charge pump/loop filter 14, a voltage controlled oscillator (VCO) 16 and a divider 18. The VCO 16 presents a signal to the divider 18. The divider 18 presents a feedback signal to the PFD 12. The PFD 12 also receives a reference clock signal CLK. The PFD generates pump signals that are proportional to the frequency and phase difference between the reference clock and the feedback signal. The pump signals are presented to the charge pump/loop filter 14. The charge pump/loop filter 14 presents two voltage control signals to the VCO 16 in response to the pump signals. The VCO 16 generates clock signals that are proportional to the voltage control signals. During normal operating conditions, the reference clock is generally synchronized with the feedback signal. Such a synchronization is shown by the block 20.
The acquisition rate of a PLL refers to the rate (MHz/.mu.S) that a PLL can acquire lock when switching from a first frequency (e.g., A) to a second frequency (e.g., B). When frequency A is equal to frequency B, the acquisition rate refers to the rate of phase re-acquisition. A typical PLL will lose lock when switching from the reference frequency A to the reference frequency B. When the PLL loses lock, the output frequency can jump. A jump in frequency can cause problems in systems that are attached to the PLL.
Applications of PLLs in modern computers may require switching between reference clocks that are at about the same frequency and have some random phase difference. In order to minimize frequency jumps when switching between such reference clocks, the acquisition rate should be as low as possible.
Referring to FIG. 2, timing diagrams illustrating the pump signals of a conventional PFD are shown. The acquisition rate is controlled by the pump signals from the PFD. During lock (REF freq=FB freq and phase) the PFD output will generate a pump up signal and a pump down signal that are minimum but equal in size (internal PFD reset). During the acquisition period (FB trying to lock to REF), one pump signal (i.e., pump down) will be minimal in size, while the other pump signal (i.e., pump up) will be large (proportional to the phase difference). The larger the pump signal, the greater the change in frequency of the VCO.
Referring to FIG. 3, a detailed block diagram illustrating a conventional PFD 30 is shown. Typically two separate clocks (i.e., a clock signal FREQ1 and a clock signal FREQ2) are fed into the PFD 30. The PFD generates PUMP_UP and PUMP_DOWN signals that are proportional to the phase and frequency differences of the incoming clocks. The PFD pump signals have identical falling edges, while the rising edge is a function of the phase difference between the signals FREQ1 and FREQ2. A rising transition of the signal FREQ1 clocks flip-flop 32 making the signal PUMP_UP HIGH. A rising transition of the signal FREQ2 clocks the flip-flop 34 making the signal PUMP_DOWN HIGH. When the signal PUMP_UP and the signal PUMP_DOWN are both HIGH, the AND gate 36 resets the flip-flops 32 and 34, returning both the signal PUMP_UP and the signal PUMP_DOWN to a LOW state. Altering one pump pulse width generally requires altering the other pump pulse width. Reducing large pulse widths can also cause reduction in the reset path.
Referring to FIG. 4, a block diagram illustrating a summary of a conventional method for adjusting the PFD pulse widths is shown. The signal REF is used to generate a reference window signal REF_WINDOW. A pulse limiter circuit truncates any portion of the pump signal that is outside the reference window signal REF_WINDOW. The size of the signal REF_WINDOW is a function of the REF_FREQUENCY. Overlap between the pump signal and the delayed reference window can impact the quality of the pump signal. The delay of the signal REF to the output must match the entire path through the PFD, which consumes excess current. The amount of truncation is a function of the delay path of the signal REF, the width of the signal REF_WINDOW, and the pump path through the PFD. The alignment of the signal REF_WINDOW created relative to the pump signals is difficult to control since it is function of the delay. Implementation requires a larger die area. Placing an extra load on the signal REF can impact the timing of the signal REF that can result in increased static phase offset.